552 lines
12 KiB
ArmAsm
552 lines
12 KiB
ArmAsm
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/*
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* Copyright (C) 2004 Axis Communications AB
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*
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* Code for handling break 8, hardware breakpoint, single step, and serial
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* port exceptions for kernel debugging purposes.
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*/
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#include <arch/hwregs/intr_vect.h>
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;; Exported functions.
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.globl kgdb_handle_exception
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kgdb_handle_exception:
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;; Create a register image of the caller.
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;;
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;; First of all, save the ACR on the stack since we need it for address calculations.
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;; We put it into the register struct later.
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subq 4, $sp
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move.d $acr, [$sp]
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;; Now we are free to use ACR all we want.
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;; If we were running this handler with interrupts on, we would have to be careful
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;; to save and restore CCS manually, but since we aren't we treat it like every other
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;; register.
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move.d reg, $acr
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move.d $r0, [$acr] ; Save R0 (start of register struct)
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addq 4, $acr
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move.d $r1, [$acr] ; Save R1
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addq 4, $acr
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move.d $r2, [$acr] ; Save R2
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addq 4, $acr
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move.d $r3, [$acr] ; Save R3
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addq 4, $acr
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move.d $r4, [$acr] ; Save R4
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addq 4, $acr
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move.d $r5, [$acr] ; Save R5
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addq 4, $acr
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move.d $r6, [$acr] ; Save R6
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addq 4, $acr
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move.d $r7, [$acr] ; Save R7
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addq 4, $acr
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move.d $r8, [$acr] ; Save R8
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addq 4, $acr
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move.d $r9, [$acr] ; Save R9
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addq 4, $acr
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move.d $r10, [$acr] ; Save R10
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addq 4, $acr
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move.d $r11, [$acr] ; Save R11
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addq 4, $acr
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move.d $r12, [$acr] ; Save R12
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addq 4, $acr
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move.d $r13, [$acr] ; Save R13
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addq 4, $acr
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move.d $sp, [$acr] ; Save SP (R14)
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addq 4, $acr
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;; The ACR register is already saved on the stack, so pop it from there.
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move.d [$sp],$r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $bz, [$acr]
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addq 1, $acr
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move $vr, [$acr]
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addq 1, $acr
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move $pid, [$acr]
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addq 4, $acr
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move $srs, [$acr]
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addq 1, $acr
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move $wz, [$acr]
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addq 2, $acr
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move $exs, [$acr]
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addq 4, $acr
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move $eda, [$acr]
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addq 4, $acr
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move $mof, [$acr]
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addq 4, $acr
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move $dz, [$acr]
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addq 4, $acr
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move $ebp, [$acr]
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addq 4, $acr
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move $erp, [$acr]
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addq 4, $acr
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move $srp, [$acr]
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addq 4, $acr
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move $nrp, [$acr]
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addq 4, $acr
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move $ccs, [$acr]
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addq 4, $acr
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move $usp, [$acr]
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addq 4, $acr
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move $spc, [$acr]
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addq 4, $acr
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;; Skip the pseudo-PC.
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addq 4, $acr
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;; Save the support registers in bank 0 - 3.
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clear.d $r1 ; Bank counter
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move.d sreg, $acr
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;; Bank 0
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move $r1, $srs
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nop
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nop
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nop
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move $s0, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s1, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s2, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s3, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s4, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s5, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s6, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s7, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s8, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s9, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s10, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s11, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s12, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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;; Nothing in S13 - S15, bank 0
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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;; Bank 1 and bank 2 have the same layout, hence the loop.
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addq 1, $r1
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1:
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move $r1, $srs
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nop
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nop
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nop
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move $s0, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s1, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s2, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s3, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s4, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s5, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s6, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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;; Nothing in S7 - S15, bank 1 and 2
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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clear.d [$acr]
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addq 4, $acr
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addq 1, $r1
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cmpq 3, $r1
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bne 1b
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nop
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;; Bank 3
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move $r1, $srs
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nop
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nop
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nop
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move $s0, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s1, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s2, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s3, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s4, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s5, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s6, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s7, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s8, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s9, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s10, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s11, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s12, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s13, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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move $s14, $r0
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move.d $r0, [$acr]
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addq 4, $acr
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;; Nothing in S15, bank 3
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clear.d [$acr]
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addq 4, $acr
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;; Check what got us here: get IDX field of EXS.
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move $exs, $r10
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and.d 0xff00, $r10
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lsrq 8, $r10
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#if defined(CONFIG_ETRAX_KGDB_PORT0)
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cmp.d SER0_INTR_VECT, $r10 ; IRQ for serial port 0
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beq sigint
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nop
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#elif defined(CONFIG_ETRAX_KGDB_PORT1)
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cmp.d SER1_INTR_VECT, $r10 ; IRQ for serial port 1
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beq sigint
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nop
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#elif defined(CONFIG_ETRAX_KGDB_PORT2)
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cmp.d SER2_INTR_VECT, $r10 ; IRQ for serial port 2
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beq sigint
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nop
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#elif defined(CONFIG_ETRAX_KGDB_PORT3)
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cmp.d SER3_INTR_VECT, $r10 ; IRQ for serial port 3
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beq sigint
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nop
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#endif
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;; Multiple interrupt must be due to serial break.
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cmp.d 0x30, $r10 ; Multiple interrupt
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beq sigint
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nop
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;; Neither of those? Then it's a sigtrap.
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ba handle_comm
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moveq 5, $r10 ; Set SIGTRAP (delay slot)
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sigint:
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;; Serial interrupt; get character
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jsr getDebugChar
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nop ; Delay slot
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cmp.b 3, $r10 ; \003 (Ctrl-C)?
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bne return ; No, get out of here
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nop
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moveq 2, $r10 ; Set SIGINT
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;;
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;; Handle the communication
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;;
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handle_comm:
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move.d internal_stack+1020, $sp ; Use the internal stack which grows upwards
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jsr handle_exception ; Interactive routine
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nop
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;;
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;; Return to the caller
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;;
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return:
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;; First of all, write the support registers.
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clear.d $r1 ; Bank counter
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move.d sreg, $acr
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;; Bank 0
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move $r1, $srs
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nop
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nop
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nop
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move.d [$acr], $r0
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move $r0, $s0
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s1
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s2
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s3
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s4
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s5
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addq 4, $acr
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;; Nothing in S6 - S7, bank 0.
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addq 4, $acr
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s8
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s9
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s10
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s11
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s12
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addq 4, $acr
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;; Nothing in S13 - S15, bank 0
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addq 4, $acr
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addq 4, $acr
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addq 4, $acr
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;; Bank 1 and bank 2 have the same layout, hence the loop.
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addq 1, $r1
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2:
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move $r1, $srs
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nop
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nop
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nop
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move.d [$acr], $r0
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move $r0, $s0
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addq 4, $acr
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move.d [$acr], $r0
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move $r0, $s1
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s2
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
;; S3 (MM_CAUSE) is read-only.
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s4
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.)
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
;; Nothing in S7 - S15, bank 1 and 2
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
addq 1, $r1
|
||
|
|
cmpq 3, $r1
|
||
|
|
bne 2b
|
||
|
|
nop
|
||
|
|
|
||
|
|
;; Bank 3
|
||
|
|
move $r1, $srs
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s0
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s1
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s2
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s3
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s4
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s5
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s6
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s7
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s8
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s9
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s10
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s11
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s12
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s13
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r0
|
||
|
|
move $r0, $s14
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
;; Nothing in S15, bank 3
|
||
|
|
addq 4, $acr
|
||
|
|
|
||
|
|
;; Now, move on to the regular register restoration process.
|
||
|
|
|
||
|
|
move.d reg, $acr ; Reset ACR to point at the beginning of the register image
|
||
|
|
move.d [$acr], $r0 ; Restore R0
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r1 ; Restore R1
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r2 ; Restore R2
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r3 ; Restore R3
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r4 ; Restore R4
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r5 ; Restore R5
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r6 ; Restore R6
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r7 ; Restore R7
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r8 ; Restore R8
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r9 ; Restore R9
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r10 ; Restore R10
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r11 ; Restore R11
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r12 ; Restore R12
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $r13 ; Restore R13
|
||
|
|
|
||
|
|
;;
|
||
|
|
;; We restore all registers, even though some of them probably haven't changed.
|
||
|
|
;;
|
||
|
|
|
||
|
|
addq 4, $acr
|
||
|
|
move.d [$acr], $sp ; Restore SP (R14)
|
||
|
|
|
||
|
|
;; ACR cannot be restored just yet.
|
||
|
|
addq 8, $acr
|
||
|
|
|
||
|
|
;; Skip BZ, VR.
|
||
|
|
addq 2, $acr
|
||
|
|
|
||
|
|
move [$acr], $pid ; Restore PID
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $srs ; Restore SRS
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
addq 1, $acr
|
||
|
|
|
||
|
|
;; Skip WZ.
|
||
|
|
addq 2, $acr
|
||
|
|
|
||
|
|
move [$acr], $exs ; Restore EXS.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $eda ; Restore EDA.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $mof ; Restore MOF.
|
||
|
|
|
||
|
|
;; Skip DZ.
|
||
|
|
addq 8, $acr
|
||
|
|
|
||
|
|
move [$acr], $ebp ; Restore EBP.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $erp ; Restore ERP.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $srp ; Restore SRP.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $nrp ; Restore NRP.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $ccs ; Restore CCS like an ordinary register.
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $usp ; Restore USP
|
||
|
|
addq 4, $acr
|
||
|
|
move [$acr], $spc ; Restore SPC
|
||
|
|
; No restoration of pseudo-PC of course.
|
||
|
|
|
||
|
|
move.d reg, $acr ; Reset ACR to point at the beginning of the register image
|
||
|
|
add.d 15*4, $acr
|
||
|
|
move.d [$acr], $acr ; Finally, restore ACR.
|
||
|
|
rete ; Same as jump ERP
|
||
|
|
rfe ; Shifts CCS
|