337 lines
8.0 KiB
C
337 lines
8.0 KiB
C
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/*
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* OpenFirmware bindings for Secure Digital Host Controller Interface.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <asm/machdep.h>
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#include "sdhci.h"
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struct sdhci_of_data {
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unsigned int quirks;
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struct sdhci_ops ops;
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};
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struct sdhci_of_host {
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unsigned int clock;
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u16 xfer_mode_shadow;
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};
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_DMA_SNOOP 0x00000040
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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#define ESDHC_HOST_CONTROL_RES 0x05
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static u32 esdhc_readl(struct sdhci_host *host, int reg)
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{
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return in_be32(host->ioaddr + reg);
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}
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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if (unlikely(reg == SDHCI_HOST_VERSION))
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ret = in_be16(host->ioaddr + reg);
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else
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ret = in_be16(host->ioaddr + (reg ^ 0x2));
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return ret;
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}
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static u8 esdhc_readb(struct sdhci_host *host, int reg)
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{
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return in_8(host->ioaddr + (reg ^ 0x3));
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}
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static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
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{
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out_be32(host->ioaddr + reg, val);
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}
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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of_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow,
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SDHCI_TRANSFER_MODE);
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return;
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case SDHCI_BLOCK_SIZE:
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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/* fall through */
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}
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clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
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}
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static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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int pre_div = 2;
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int div = 1;
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clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
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if (clock == 0)
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goto out;
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while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
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pre_div *= 2;
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while (host->max_clk / pre_div / div > clock && div < 16)
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div++;
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->max_clk / pre_div / div);
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pre_div >>= 1;
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div--;
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setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
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div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
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mdelay(100);
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out:
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host->clock = clock;
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}
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static int esdhc_enable_dma(struct sdhci_host *host)
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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return 0;
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}
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static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock;
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}
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static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock / 256 / 16;
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}
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static struct sdhci_of_data sdhci_esdhc = {
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.quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
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SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_NO_BUSY_IRQ |
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SDHCI_QUIRK_NONSTANDARD_CLOCK |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_PIO_NEEDS_DELAY |
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SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
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SDHCI_QUIRK_NO_CARD_NO_RESET,
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.ops = {
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.readl = esdhc_readl,
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.readw = esdhc_readw,
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.readb = esdhc_readb,
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.writel = esdhc_writel,
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.writew = esdhc_writew,
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.writeb = esdhc_writeb,
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.set_clock = esdhc_set_clock,
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.enable_dma = esdhc_enable_dma,
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.get_max_clock = esdhc_get_max_clock,
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.get_min_clock = esdhc_get_min_clock,
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},
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};
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#ifdef CONFIG_PM
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static int sdhci_of_suspend(struct of_device *ofdev, pm_message_t state)
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{
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struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
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return mmc_suspend_host(host->mmc, state);
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}
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static int sdhci_of_resume(struct of_device *ofdev)
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{
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struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
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return mmc_resume_host(host->mmc);
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}
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#else
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#define sdhci_of_suspend NULL
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#define sdhci_of_resume NULL
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#endif
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static bool __devinit sdhci_of_wp_inverted(struct device_node *np)
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{
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if (of_get_property(np, "sdhci,wp-inverted", NULL))
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return true;
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/* Old device trees don't have the wp-inverted property. */
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return machine_is(mpc837x_rdb) || machine_is(mpc837x_mds);
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}
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static int __devinit sdhci_of_probe(struct of_device *ofdev,
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const struct of_device_id *match)
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{
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struct device_node *np = ofdev->node;
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struct sdhci_of_data *sdhci_of_data = match->data;
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struct sdhci_host *host;
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struct sdhci_of_host *of_host;
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const u32 *clk;
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int size;
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int ret;
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if (!of_device_is_available(np))
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return -ENODEV;
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host = sdhci_alloc_host(&ofdev->dev, sizeof(*of_host));
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if (IS_ERR(host))
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return -ENOMEM;
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of_host = sdhci_priv(host);
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dev_set_drvdata(&ofdev->dev, host);
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host->ioaddr = of_iomap(np, 0);
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if (!host->ioaddr) {
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ret = -ENOMEM;
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goto err_addr_map;
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}
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host->irq = irq_of_parse_and_map(np, 0);
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if (!host->irq) {
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ret = -EINVAL;
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goto err_no_irq;
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}
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host->hw_name = dev_name(&ofdev->dev);
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if (sdhci_of_data) {
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host->quirks = sdhci_of_data->quirks;
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host->ops = &sdhci_of_data->ops;
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}
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if (of_get_property(np, "sdhci,1-bit-only", NULL))
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host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
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if (sdhci_of_wp_inverted(np))
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host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
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clk = of_get_property(np, "clock-frequency", &size);
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if (clk && size == sizeof(*clk) && *clk)
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of_host->clock = *clk;
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ret = sdhci_add_host(host);
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if (ret)
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goto err_add_host;
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return 0;
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err_add_host:
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irq_dispose_mapping(host->irq);
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err_no_irq:
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iounmap(host->ioaddr);
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err_addr_map:
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sdhci_free_host(host);
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return ret;
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}
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static int __devexit sdhci_of_remove(struct of_device *ofdev)
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{
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struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
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sdhci_remove_host(host, 0);
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sdhci_free_host(host);
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irq_dispose_mapping(host->irq);
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iounmap(host->ioaddr);
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return 0;
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}
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static const struct of_device_id sdhci_of_match[] = {
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{ .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, },
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{ .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, },
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{ .compatible = "fsl,esdhc", .data = &sdhci_esdhc, },
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{ .compatible = "generic-sdhci", },
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{},
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};
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MODULE_DEVICE_TABLE(of, sdhci_of_match);
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static struct of_platform_driver sdhci_of_driver = {
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.driver.name = "sdhci-of",
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.match_table = sdhci_of_match,
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.probe = sdhci_of_probe,
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.remove = __devexit_p(sdhci_of_remove),
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.suspend = sdhci_of_suspend,
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.resume = sdhci_of_resume,
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};
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static int __init sdhci_of_init(void)
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{
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return of_register_platform_driver(&sdhci_of_driver);
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}
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module_init(sdhci_of_init);
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static void __exit sdhci_of_exit(void)
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{
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of_unregister_platform_driver(&sdhci_of_driver);
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}
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module_exit(sdhci_of_exit);
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MODULE_DESCRIPTION("Secure Digital Host Controller Interface OF driver");
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MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
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"Anton Vorontsov <avorontsov@ru.mvista.com>");
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MODULE_LICENSE("GPL");
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