332 lines
7.2 KiB
C
332 lines
7.2 KiB
C
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/*
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* arch/m68k/q40/config.c
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*
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* Copyright (C) 1999 Richard Zidlicky
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*
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* originally based on:
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*
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* linux/bvme/config.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file README.legal in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/console.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/major.h>
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#include <linux/serial_reg.h>
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#include <linux/rtc.h>
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#include <linux/vt_kern.h>
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#include <linux/bcd.h>
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#include <asm/io.h>
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#include <asm/rtc.h>
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#include <asm/bootinfo.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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#include <asm/q40_master.h>
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extern void q40_init_IRQ(void);
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static void q40_get_model(char *model);
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extern void q40_sched_init(irq_handler_t handler);
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static unsigned long q40_gettimeoffset(void);
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static int q40_hwclk(int, struct rtc_time *);
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static unsigned int q40_get_ss(void);
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static int q40_set_clock_mmss(unsigned long);
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static int q40_get_rtc_pll(struct rtc_pll_info *pll);
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static int q40_set_rtc_pll(struct rtc_pll_info *pll);
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extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
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static void q40_mem_console_write(struct console *co, const char *b,
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unsigned int count);
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extern int ql_ticks;
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static struct console q40_console_driver = {
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.name = "debug",
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.write = q40_mem_console_write,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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};
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/* early debugging function:*/
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extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
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static int _cpleft;
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static void q40_mem_console_write(struct console *co, const char *s,
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unsigned int count)
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{
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const char *p = s;
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if (count < _cpleft) {
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while (count-- > 0) {
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*q40_mem_cptr = *p++;
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q40_mem_cptr += 4;
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_cpleft--;
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}
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}
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}
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static int __init q40_debug_setup(char *arg)
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{
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/* useful for early debugging stages - writes kernel messages into SRAM */
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if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
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/*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
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_cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
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register_console(&q40_console_driver);
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}
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return 0;
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}
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early_param("debug", q40_debug_setup);
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#if 0
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void printq40(char *str)
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{
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int l = strlen(str);
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char *p = q40_mem_cptr;
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while (l-- > 0 && _cpleft-- > 0) {
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*p = *str++;
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p += 4;
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}
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q40_mem_cptr = p;
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}
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#endif
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static int halted;
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#ifdef CONFIG_HEARTBEAT
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static void q40_heartbeat(int on)
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{
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if (halted)
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return;
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if (on)
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Q40_LED_ON();
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else
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Q40_LED_OFF();
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}
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#endif
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static void q40_reset(void)
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{
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halted = 1;
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printk("\n\n*******************************************\n"
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"Called q40_reset : press the RESET button!! \n"
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"*******************************************\n");
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Q40_LED_ON();
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while (1)
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;
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}
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static void q40_halt(void)
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{
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halted = 1;
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printk("\n\n*******************\n"
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" Called q40_halt\n"
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"*******************\n");
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Q40_LED_ON();
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while (1)
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;
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}
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static void q40_get_model(char *model)
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{
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sprintf(model, "Q40");
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}
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static unsigned int serports[] =
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{
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0x3f8,0x2f8,0x3e8,0x2e8,0
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};
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static void q40_disable_irqs(void)
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{
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unsigned i, j;
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j = 0;
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while ((i = serports[j++]))
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outb(0, i + UART_IER);
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master_outb(0, EXT_ENABLE_REG);
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master_outb(0, KEY_IRQ_ENABLE_REG);
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}
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void __init config_q40(void)
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{
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mach_sched_init = q40_sched_init;
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mach_init_IRQ = q40_init_IRQ;
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mach_gettimeoffset = q40_gettimeoffset;
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mach_hwclk = q40_hwclk;
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mach_get_ss = q40_get_ss;
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mach_get_rtc_pll = q40_get_rtc_pll;
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mach_set_rtc_pll = q40_set_rtc_pll;
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mach_set_clock_mmss = q40_set_clock_mmss;
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mach_reset = q40_reset;
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mach_get_model = q40_get_model;
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#if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
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mach_beep = q40_mksound;
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#endif
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#ifdef CONFIG_HEARTBEAT
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mach_heartbeat = q40_heartbeat;
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#endif
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mach_halt = q40_halt;
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/* disable a few things that SMSQ might have left enabled */
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q40_disable_irqs();
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/* no DMA at all, but ide-scsi requires it.. make sure
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* all physical RAM fits into the boundary - otherwise
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* allocator may play costly and useless tricks */
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mach_max_dma_address = 1024*1024*1024;
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}
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int q40_parse_bootinfo(const struct bi_record *rec)
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{
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return 1;
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}
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static unsigned long q40_gettimeoffset(void)
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{
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return 5000 * (ql_ticks != 0);
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}
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/*
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* Looks like op is non-zero for setting the clock, and zero for
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* reading the clock.
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*
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* struct hwclk_time {
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* unsigned sec; 0..59
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* unsigned min; 0..59
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* unsigned hour; 0..23
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* unsigned day; 1..31
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* unsigned mon; 0..11
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* unsigned year; 00...
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* int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
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* };
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*/
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static int q40_hwclk(int op, struct rtc_time *t)
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{
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if (op) {
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/* Write.... */
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Q40_RTC_CTRL |= Q40_RTC_WRITE;
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Q40_RTC_SECS = bin2bcd(t->tm_sec);
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Q40_RTC_MINS = bin2bcd(t->tm_min);
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Q40_RTC_HOUR = bin2bcd(t->tm_hour);
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Q40_RTC_DATE = bin2bcd(t->tm_mday);
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Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
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Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
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if (t->tm_wday >= 0)
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Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
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Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
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} else {
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/* Read.... */
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Q40_RTC_CTRL |= Q40_RTC_READ;
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t->tm_year = bcd2bin (Q40_RTC_YEAR);
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t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
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t->tm_mday = bcd2bin (Q40_RTC_DATE);
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t->tm_hour = bcd2bin (Q40_RTC_HOUR);
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t->tm_min = bcd2bin (Q40_RTC_MINS);
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t->tm_sec = bcd2bin (Q40_RTC_SECS);
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Q40_RTC_CTRL &= ~(Q40_RTC_READ);
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if (t->tm_year < 70)
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t->tm_year += 100;
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t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
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}
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return 0;
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}
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static unsigned int q40_get_ss(void)
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{
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return bcd2bin(Q40_RTC_SECS);
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}
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/*
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* Set the minutes and seconds from seconds value 'nowtime'. Fail if
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* clock is out by > 30 minutes. Logic lifted from atari code.
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*/
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static int q40_set_clock_mmss(unsigned long nowtime)
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{
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int retval = 0;
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short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
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int rtc_minutes;
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rtc_minutes = bcd2bin(Q40_RTC_MINS);
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if ((rtc_minutes < real_minutes ?
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real_minutes - rtc_minutes :
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rtc_minutes - real_minutes) < 30) {
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Q40_RTC_CTRL |= Q40_RTC_WRITE;
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Q40_RTC_MINS = bin2bcd(real_minutes);
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Q40_RTC_SECS = bin2bcd(real_seconds);
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Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
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} else
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retval = -1;
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return retval;
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}
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/* get and set PLL calibration of RTC clock */
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#define Q40_RTC_PLL_MASK ((1<<5)-1)
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#define Q40_RTC_PLL_SIGN (1<<5)
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static int q40_get_rtc_pll(struct rtc_pll_info *pll)
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{
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int tmp = Q40_RTC_CTRL;
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pll->pll_value = tmp & Q40_RTC_PLL_MASK;
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if (tmp & Q40_RTC_PLL_SIGN)
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pll->pll_value = -pll->pll_value;
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pll->pll_max = 31;
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pll->pll_min = -31;
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pll->pll_posmult = 512;
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pll->pll_negmult = 256;
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pll->pll_clock = 125829120;
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return 0;
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}
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static int q40_set_rtc_pll(struct rtc_pll_info *pll)
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{
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if (!pll->pll_ctrl) {
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/* the docs are a bit unclear so I am doublesetting */
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/* RTC_WRITE here ... */
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int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
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Q40_RTC_WRITE;
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Q40_RTC_CTRL |= Q40_RTC_WRITE;
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Q40_RTC_CTRL = tmp;
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Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
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return 0;
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} else
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return -EINVAL;
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}
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